Junior Digital Design Engineer - Brno
RTL / HDLFPGAPosted Oct 20, 2026
Overview
- Added in 30 days
- 4
- At this company, still open
Skills named in this posting
- SystemVerilog
- Verilog
- VHDL
- C
- C++
Job Title:
Junior Digital Design Engineer
Job Level:
Entry- to Mid-level
Term:
Full Time
Work Authorization:
European Union or Foreign Citizen
Degree:
MS in Electrical Engineering or Computer Science
Location:
Brno, Czech Republic
Travel:
Little to none
This is a new full-time, engineering position for candidates with academic or some industry experience with digital IC design.
We are now expanding our engineering team located in Brno, Czech Republic, where we focus on IP core development in the areas like bus interfaces, network protocols, multimedia and automotive applications. In this position, you will help develop and productize new IP cores.
Responsibilities
• The design and verification of digital IP cores.
• Integrating the IP cores in system or subsystem reference designs.
• Implementing and evaluating the reference designs in FPGAs.
Requirements
• MS degree in Electrical Engineering, Computer Science, or a related field; or 2–3 years of professional digital design experience.
• Fluency in written and spoken English.
• Understanding of digital design concepts.
• Experience with Verilog, System Verilog, or VHDL at least at the FPGA level.
• Experience with simulation and verification in Modelsim or similar tools.
• Pluses include knowledge of scripting languages like TCL and shells; experience coding with C/C++; and embedded processor knowledge.
Apply on the employer's site
Original posting: cast-inc.com
RISC-V ecosystem
CAST, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
CAST is a 20+ year successful provider of reusable semiconductor intellectual property (IP) cores and subsystems for electronic system designers.
- Licenses RISC-V processor IP cores: "These IP cores make adopting RISC-V simple, quick, and with less technical and budget risk"
- RISC-V lineup includes the Catalyst program of pre-configured embedded RISC-V cores
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