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Signal and Power Integrity Engineer

NVIDIA Corporation

US, CA, Santa Clara, US, TX, AustinSoC / ASICPosted Mar 17, 2026
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Skills named in this posting

  • Mixed-signal
  • USB
  • Python
We are now looking for a Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle! What you'll be doing: • Work on crafting creative Signal Integrity solutions to complex system design problems. • Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D EM tools. • System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, LP5X and other interfaces. • Constant improvements of SI models using data from lab measurements and/or modelling tool/methodology updates. • Substrate and board layout SI guidelines creation, review and post layout SI extractions. • Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools. • Opportunity to work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit. What we need to see: • MS and/or PhD in Electrical and Computer Engineering (or equivalent experience) with minimum 2 years of work experience • Strong technical background in applied electromagnetics, waveguides, transmission line theory and signal processing will be highly valued. • Familiarity with signal and power integrity concepts, design and analysis. • Exposure to channel SI time domain simulations. • Hands on use of 3-D modeling tools like ANSYS HFSS/Q3D, 2.5-D with ANSYS SIWAVE or similar and 2D such as Ansys2D. • Familiarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro. • Scripting skills for data post-processing, tool development and/or process automation Ways to stand out from the crowd: • Exposure to board/pkg technology & design. • Understanding of circuit equalization techniques. • Exposure to PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations. • Knowledge of programming language(s), especially Python NVIDIA is widely considered one of the technology world’s most desirable employers. We employ some of the most forward-thinking and talented people in the world. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until March 21, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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Original posting: jobs.nvidia.com

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RISC-V ecosystem

NVIDIA Corporation in the RISC-V ecosystem

RISC-V International: Premier Board

Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.

  • NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
  • Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
  • Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage

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