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Design Engineer II

Cadence Design Systems, Inc.

SHANGHAIPhysical designPosted Oct 27, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities: Focus on high speed digital DDR and HBM IP physical implementation Job Requirement: 1. Have good physical design experiences in the digital implementation domain including Floorplan, P&R, Physical verification, DFM. 2. Have a solid background in circuits, electronics & physics & should be very willing to learn new technology for advance node and design methodology 3. Skilled in scripting language, such as Perl, C shell, Makefile 4. Feeling responsible for technical delivery, good team played, design quality/schedule focus We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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