Principal Engineer

We are looking for an experienced SoC/IP Verification Engineer to lead and drive the verification of complex semiconductor designs. The role involves defining verification strategies, architecting and developing scalable constraint-random verification environments, and driving verification closure at both subsystem and SoC levels. The ideal candidate will possess strong expertise in System Verilog/UVM-based verification methodologies and hands-on experience across functional, power-aware, and gate-level verification flows. Your role Key responsibilities in your new role • Lead and contribute to the definition of verification architecture and strategy for IPs, subsystems, and SoCs. • Develop robust constraint-random verification environments from scratch using SystemVerilog and UVM methodologies. • Build reusable verification components, assertions, coverage models, and testbenches to ensure comprehensive design validation. • Verify ARM-based IPs and SoCs with strong understanding of AHB, AXI, and serial communication protocols. • Perform RTL verification, power-aware simulations, Gate-Level Simulations (GLS), boot verification, and drive end-to-end verification closure. • Develop C-based tests, debug complex functional issues using Tarmac, and collaborate closely with design and software teams. • Drive automation initiatives to improve verification productivity, coverage, and quality. • Mentor and guide junior engineers while promoting verification best practices across the team. Your profile Qualifications and skills to help you succeed • Strong expertise in Verilog/SystemVerilog, UVM, C programming, and Tarmac debugging. • Proven experience in IP and SoC verification, including verification planning, component development, assertion coding, and constrained-random verification. • Experience leading or contributing to the development of verification architectures and UVM environments from scratch at subsystem and SoC levels. • Hands-on experience in RTL verification, Power-Aware Verification, Gate-Level Simulation (GLS), and Boot Verification. • Strong knowledge of ARM-based architectures, AHB/AXI protocols, and industry-standard serial interfaces. • Experience with verification automation, coverage closure, regression management, and verification signoff activities. • Strong analytical, debugging, leadership, and stakeholder management skills. • Ability to mentor engineers and drive verification excellence on complex SoC programs. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Anand Rawal