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Intern on AMS tool in Milan

Cadence Design Systems, Inc.

MILANVerificationSoC / ASICPosted Sep 21, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • Mixed-signal
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Internship in the Milan office for Engineering student Subject of the internship: Real Number Models (RNMs) are behavioral models of analog circuits that use real-valued variables instead of solving transistor-level equations. They are widely used for mixed-signal SoC verification because they run on the digital simulation engine and are typically 100×–1000× faster than SPICE simulations. The intern will investigate the usage of generative AI to accelerate the verification of new semiconductors designs. Working on real industry cases, you will collaborate to define and validate new AI driven design flows which will increase the productivity of the design teams. The intern will use/validate Model In Minutes flow being integrated into Virtuoso to build the Real Number Models. Multinational environment and connection with various teams. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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