Verification Engineering Lead/Manager

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM/RISC-V processor technology and AMBA AHB/AXI/APB along with high-speed interfaces like PCIe, MIPI, USB, Ethernet, Mobile DDR and Quad/Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN, Ethernet, PCIe, UCIe as well as Mixed Signal AMS simulation environment. Role and Responsibility • Lead the SOC and Mixed signal verification team and efforts • Build capable verification team and manage the tasks and the team to get to tape out on agreed upon schedule and to Production with Agreed upon turns. Revision 0 Silicon success is highly desired. • Develop and signoff on test plans and test cases • Strong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces. • strong knowledge of Verilog, System Verilog, UVM, C/C++ • Experience in usage of assertions, constrained random generation, functional/code coverage • Knowledge of scripting languages like Perl, Python, TCL, Linux shells to achieve automation of verification methodologies and flows • Analytical debugging skills • Excellent team building and management skills Qualifications and Experience • BS in EE with 8+ years of experience or MS in EE with 6+ year experience • Knowledge of at least one of high-speed interfaces like USB, MIPI, PCIe, Ethernet, DP, • Knowledge of two or three of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, SPI • Experience managing a verification team • Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti • Fluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog • Experience in writing Test-plans and creating directed and random test cases • Strong scripting skills in Perl, Python, Linux shells etc. • Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure • Strong analytical problem solving and attention to details • Team player with interest in filing up gaps in product development as needed • Good written and verbal communication skills • Good technical documentation skills • Good interpersonal skills, self-motivated, self-starter Expectations • Develop the Test benchses for AMS and FC simulations • Be UPF Aware. • Develop the tests to get 95+% coverage for the simulations • Work with Design team to debug any failures • Integrate and run the BIST and DFT gate level sims. • Do code, line and toggle coverage and other metrics. • Run daily and weekly regressions and publish results • Responsible for FC RTL, Gate level simulations • Be a mentor and lead a team of Verification engineers • Work with Systems and Test engineering team to help validate the parts and release them to production