Silicon Design Engineer (1 year contract)

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. About the Department Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.   THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: • Understand Design-for-Test (DFT) architecture • Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem • Setup and execute design checks using both industry standard and in-house tools • Deliver Perl, Python, TCL scripts that provide scalable solutions key to DFT implementation • Monitor CAD and/or IP regression results, debug failures and analyze coverage • Develop in-house automation, utilities, intranet web portal, AI/ML applications PREFERRED EXPERIENCE: • Experience with Perl/Python/Shell scripting, C++, SQL • Experience with AI/ML application • Good object oriented programming skills • Digital circuits and VLSI knowledge • Strong problem solving skills • Good written and oral communication skills • Team player with strong interpersonal skills ACADEMIC CREDENTIALS: • Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-CC4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. About the Department Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.   THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: • Understand Design-for-Test (DFT) architecture • Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem • Setup and execute design checks using both industry standard and in-house tools • Deliver Perl, Python, TCL scripts that provide scalable solutions key to DFT implementation • Monitor CAD and/or IP regression results, debug failures and analyze coverage • Develop in-house automation, utilities, intranet web portal, AI/ML applications PREFERRED EXPERIENCE: • Experience with Perl/Python/Shell scripting, C++, SQL • Experience with AI/ML application • Good object oriented programming skills • Digital circuits and VLSI knowledge • Strong problem solving skills • Good written and oral communication skills • Team player with strong interpersonal skills ACADEMIC CREDENTIALS: • Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-CC4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.