SOC DFT Engineer

1.Responsible for SOC chip-level and sub-system level DFT architecture definition, scan insertion, scan timing constraint, ATPG pattern generation/simulation, ATPG post-silicon diagnosis, MP support and etc. 2.Support chip-level/sub-system DFT related check and implementation, including ATPG DRC, ATPG coverage improve, ATPG pattern count reduction, Equivalence check, Scan SDC constraint, Timing Sign-off, Timing ECO, Power Analysis, and other scan related performance/power/area quality boost, etc. 3.Support SOC physical implementation for DFT part, and support TE for MP issue.