RTL Design Manager

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: • AMD is seeking a capable and motivated SOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices • You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products • This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis. • You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects THE PERSON: • Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution KEY RESPONISIBILITES: • Team management (hiring, coaching, reviewing and retaining engineers) • Project Planning • Tracking Project Execution and reporting of key metrics • Managing Design reviews around feature and quality • Retrospectives and project wind-down • Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management) • Participate in tapeout checklists and reviews • Improve processes for team through AI adoption and traditional automation REQUIRED EXPERIENCE: • EngineeringDigital design and experience with RTL design in Verilog/System VerilogSolid understanding of DFT technologies and some experience with execution of DFT flowsExperience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulationExperience in specifying timing constraints with several clock domains and modesBasic experience with Synopsys Design Compiler and PrimetimeExperience designing with multiple power domains and islands using UPFTCL, Python, Perl scriptingVersion control systems such as Perforce, IC Manage or GitFluent in working with Linux and Windows environments • Leadership/ManagementStrong verbal and written communication skillsAbility to organize and present complex technical informationProject planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple timezonesTeam building experience Academic Credentials and Experience • Bachelors or Masters degree in Electrical Engineering with 12+ years of experience. #LI-PP2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: • AMD is seeking a capable and motivated SOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices • You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products • This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis. • You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects THE PERSON: • Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution KEY RESPONISIBILITES: • Team management (hiring, coaching, reviewing and retaining engineers) • Project Planning • Tracking Project Execution and reporting of key metrics • Managing Design reviews around feature and quality • Retrospectives and project wind-down • Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management) • Participate in tapeout checklists and reviews • Improve processes for team through AI adoption and traditional automation REQUIRED EXPERIENCE: • EngineeringDigital design and experience with RTL design in Verilog/System VerilogSolid understanding of DFT technologies and some experience with execution of DFT flowsExperience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulationExperience in specifying timing constraints with several clock domains and modesBasic experience with Synopsys Design Compiler and PrimetimeExperience designing with multiple power domains and islands using UPFTCL, Python, Perl scriptingVersion control systems such as Perforce, IC Manage or GitFluent in working with Linux and Windows environments • Leadership/ManagementStrong verbal and written communication skillsAbility to organize and present complex technical informationProject planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple timezonesTeam building experience Academic Credentials and Experience • Bachelors or Masters degree in Electrical Engineering with 12+ years of experience. #LI-PP2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.