Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer (f/m/d)

About us We see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connects About our technology The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution The Role We are seeking an experienced Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer to take technical ownership of the complete tape-out flow — from GDS database integration and mask data preparation through mask release, first silicon bring-up, and post-tapeout support. In this role, you will drive EIC+PIC DfX co-integration (Design for Functionality, Manufacturing, Test, Packaging, and Reliability) across a 300 mm graphene photonics platform, ensuring seamless alignment between design, fabrication, testing, and packaging requirements throughout the development cycle. To join our team, you should be excited to: - Own the complete tape-out flow including Mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign-off, and rule file maintenance for PIC-EIC integration and new process nodes. - Lead GDS and reticle-to-fab delivery, formal mask release activities, and ensure all layers, formats, and data structures comply with fab specifications. - Drive DFM and DFT integration through yield optimization, hotspot mitigation, layout optimization, and implementation of scan chains, test pads, and optical probe structures within GDS. - Design and integrate special GDS structures including kerf, seal ring, frame, scanner marks, metrology & PCM structures, ESD protection layouts, and RDL packaging interfaces. - Act as the primary interface between mask shops, foundry lithography/metrology teams, EDA vendors, and cross-functional analog, digital, packaging, and reliability teams across global regions. - Maintain GDS version control and audit-trail archiving while supporting first-silicon debug, layout-based failure analysis, and continuous improvement of MDP best practices. Your Qualifications - MS or PhD in Electrical Engineering, Physics, or a related field, with 5+ years of experience in semiconductor or photonics tape-out, layout integration, and Mask Data Preparation (MDP). - Strong expertise in GDSII/OASIS, DRC/LVS/ERC verification flows, and industry-standard tools such as Calibre and Synopsys ICV, including MDP job deck authoring and JDV (Jobdeck View). - Hands-on experience with production tape-out flows including DFM, DFT, ESD, seal ring/kerf, and RDL layout implementation. - Familiarity with OPC flows for advanced photonics or CMOS nodes and experience coordinating with mask shops and foundry partners. - Experience with Photonic IC technologies (Si, SiN, etc.), graphene or 2D-material integration, RF photonics, or photonic/electronic co-design EDA tools such as Cadence EPIC or Lumerical is considered a plus. - Background in mask shops or EDA software environments (e.g. Synopsys, Siemens, Cadence, Toppan, Photronics, Compugraphics, Tekscend) is highly desirable. Our work culture People Over Processes. At Black Semiconductor, flexibility is key—we ensure work adapts to life, not the other way around. We champion work-life harmony, where careers are meaningful and enriching. Our processes are human-centric, allowing you to focus on what matters Let’s grow together. Your potential is our priority. We provide the autonomy to make a lasting impact and nurture your growth through a culture of continuous learning. We invest in your journey for professional and personal development Your Health and Future Matter. Your well-being is paramount. We offer a comprehensive benefits package with outstanding insurance, pension and virtual stock options for your mental, physical, and financial health. Your peace of mind is our priority - in the present and future We Live Openness. Collaboration and inclusivity are the cornerstones of our culture. We practice openness, fostering trust and respect. Individuality is our collective strength, fueling innovation and driving us forward We connect chips – and people. We encourage qualified individuals from any background to apply. We foster an inclusive and supportive work environment that values collaboration, innovation, and growth. Join our team and be part of an organization dedicated to making a difference in the industry Can you picture yourself in this Role and our Company? Let’s connect! If your application results in an employment relationship, your Applicant Data will be transferred to our personnel records and processed in accordance with applicable legal requirements; otherwise, your Applicant Data will be retained for up to six (6) months after completion of the recruitment process. Read more about our privacy policy here. https://www.blacksemi.com/privacy-policy