Design Verification Engineer
Overview
Skills named in this posting
- Verilog
- x86
- C++
- Python
- Perl
Key Qualifications
• Preferably BE/B.Tech/ME/M.Tech in EEE/ECE/CSE with 5-12 years of relevant industry experience.
• Should have experience in verification methodology.
• Architecting and development of testbench, test-bench components for ISA features, clock/reset/power features of processor.
• Strong assembly and CPU (x86/ARM/RISC-V) architecture knowledge.
• Strong in C, C++, Verilog, and scripting (Perl, Python) languages.
• Ability to work independently and across geographies
Apply on the employer's site
Original posting: careers.mediatek.com
RISC-V ecosystem
MediaTek Inc in the RISC-V ecosystem
RISC-V International: Strategic
We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.
- Named in coverage of RISE, the Linux Foundation Europe RISC-V Software Ecosystem project, and RISC-V edge-AI market analysis
- Listed on the landscape as a RISC-V International member
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