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Lead Physical Design Engineer

Cadence Design Systems, Inc.

NanjingPhysical designPosted Oct 13, 2026
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Skills named in this posting

  • STA
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Physical Implementation Engineer Job Description: - A role of block/chip level physical design engineer; - Job content includes: - Physical Design, including: floorplan, placement, CTS, routing, etc. ; - Physical Verification; - Static Timing Analysis; - EM/IR Analysis. Job Qualification: - Rich knowledge of the design rule for the process of N28/N16 and below; - Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.; - Experience in chip level physical verification is preferred; - Basic knowledge/experience of the physical implementation and static timing analysis; - Bachelor or above degree in majors of EE/CS/IT, with more than 3 years’ work experience; - Good ability of effective learning and independent thinking; - Good ability of communication and teamwork; - Carefulness, responsibility and persistence. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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