Lead Product Engineer
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- DFT
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is looking for a highly motivated engineer to work with the Modus Test Product Engineering team working on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG).
What You'll Be Doing
• Be part of a team that is going to help drive new product features in DFT & ATPG
• Develop product spec, prototype and work closely with R&D & Product Validation teams in implementation & validation of such features
• Work with field team and customers in helping deploy Modus by developing flows, presentations & hands-on debug
What We Need To See
• BS (or equivalent experience) with 6+ years or MS with 4+ years of direct experience in DFT either in EDA, CAD or design implementation
• Solid understanding of ATPG, Scan, JTAG, IEEE 1687 (iJTAG), MBIST & LBIST
• Need to be aware of latest technologies & innovations in DFT both in EDA and implementation
• Experience in STA, Physical Design, Silicon bringup related to DFT is a plus
• Flexibility/adaptability for working in a highly dynamic environment and engaging with key stakeholders across various teams within and outside of Cadence
• Excellent communication, interpersonal and customer collaboration skills
Ways To Stand Out From The Crowd
• Broad knowledge of DFT domain & how DFT interacts with various other VLSI domains
• Hands-on experience with DFT EDA tools in the industry
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
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