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Sr Principal Software Engineer

Cadence Design Systems, Inc.

GYEONGGI-DO (Seoul)RTL / HDLPosted Sep 21, 2026
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Skills named in this posting

  • SystemVerilog
  • Verilog
  • AMBA / AXI
  • C
  • C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Overview: This role will contribute directly to the development and enhancement of AMBA Performance verification and/or Unipro stack products, focusing on protocol functionality, performance, and robustness. Depending on the specific protocol area, the work may involve: • Implementing AMBA protocol features and state machines • Enhancing performance and scalability on emulation platforms • Developing debug, trace, and analysis capabilities • Working with customers and field teams to resolve issues and deliver solutions related to AMBA (CHI*, ACE, AXI) Job Responsibilities: • Designing and implementing protocol functionality in AMBA AVIP • Developing and debugging BFMs, transactors, and associated software interfaces • Ensuring correctness, performance, and scalability in emulation and acceleration flows • Collaborating with cross‑functional teams • Participating in feature bring‑up, regression, and release activities • Supporting customer issues, reproducing problems, and delivering fixes • GUI based performance analysis tool development • Job Qualifications: • Strong fundamentals in digital design, computer architecture, and system‑level verification • Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++ • Understanding of standard interconnect and bus architectures (e.g., AMBA, UFS/Unipro/MPhy) • Familiarity with emulation, acceleration, or hybrid verification flows is a strong plus • Good debugging skills using waveforms, logs, and protocol analyzers • Ability to work across hardware and software boundaries We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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