SoC Physical Designer

As a Graduate Physical Design Engineer, you will participate in the development of advanced semiconductor products and be involved in the complete physical implementation flow. Your responsibilities include: • Support SoC and subsystem physical design implementation from netlist to GDSII. • Participate in floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and chip finishing activities. • Perform timing, power, signal integrity, and physical verification analysis. • Debug design implementation issues and drive convergence toward project PPAC (Performance, Power, Area, Cost) targets. • Work with cross-functional teams including RTL Design, DFT, Verification, IP, Package, and Technology teams. • Develop and improve EDA automation scripts using Python, Tcl, or other scripting languages. • Explore AI-assisted design methodologies to improve engineering productivity and design quality. • Support silicon bring-up, design reviews, and tapeout activities. • Contribute to continuous improvement of backend methodologies, flows, and best practices. Qualifications： • Master's degree (graduating in 2027) in:MicroelectronicsIntegrated Circuit DesignElectronic EngineeringComputer EngineeringAutomationRelated disciplines • Basic knowledge of VLSI design flow and semiconductor fundamentals. • Familiarity with Linux/Unix environments. • Programming experience in Python, Tcl, Perl, Shell, or C/C++. • Strong analytical and problem-solving skills. • Good communication and teamwork skills. • Fluent written and spoken English. Preferred • Coursework or project experience in:ASIC/SoC DesignPhysical DesignTiming AnalysisDFTDigital IC Design • Hands-on experience with EDA tools such as:Synopsys Fusion CompilerICC2PrimeTimeCadence InnovusTempusCalibre • Experience with machine learning or AI applications in semiconductor design. • Publications, competitions, or research projects related to EDA or IC design are a plus. More information about NXP in Greater China... #LI-6650