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Intern-Product Validation

Cadence Design Systems, Inc.

SHANGHAIPosted Sep 21, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • Place and route
  • Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Position Description are: a) Assist in Cadence innovus development and validation. b) Validate and maintain comprehensive hierarchical solution unit and flow test cases for Innovus Digital Implementation System. c) Develop test suites of the new features of functional/flow solution. The Position Requirements are: a) MS in microelectronics, EE and related majors. b) Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus. c) Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus. d) Good communication in English and Chinese, good confidence and self-motivation. **Prefer to work 3-4 days per week for 6+ months. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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