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Sr Principal Product Engineer - Innovus

Cadence Design Systems, Inc.

GYEONGGI-DO (Seoul)Physical designPosted Oct 13, 2026
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  • Place and route
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. • Candidate is required to work with foundry companies and their mutual customers by providing foundry enablement solution. • Playing as Chip-level physical implementation experts in foundry reference flow validation and in-design flow correlation and its validation. • Playing as Routing enablement (P&R techfile) experts and its validation • Candidate should have overall design flow understanding including Sign-off. • Physical implementation and P&R techfile-related issues between customers and corporate R&D are the major responsibility. • Providing Cadence physical implementation tool solution in a timely manner as a • Product Engineer and working closely with the customer on-site and off-site. • Interfacing with headquarters R&D and other Product Engineer at different sites to resolve any technical issues. • Around 13+ year professional experience (Master's degree) or 15+ year (Bachelor's degree) • Mostly worked on the physical implementation (P&R) domain and P&R techfile creation & validation • In-depth usage experience on dominant P&R tool (Innovus or ICC) • Good hands-on physical implementation area on advanced technology nodes beyond 28nm • Good communication skills internally with team members and externally with customers • Speaking/writing proficiency in English We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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