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Principal Software Engineer

Cadence Design Systems, Inc.

PUNE 04RTL / HDLCompilersFirmwarePosted Oct 8, 2026
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Skills named in this posting

  • Emulation
  • Python
  • PyTorch / TensorFlow
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Automation Framework Ownership • Own, maintain, and enhance the end-to-end automation flow used to:Compile neural networks using the XNNC compiler.Run generated RTL binaries on Palladium Z3 emulation.Drive Joules gate-level power analysis. • Develop and maintain the Python, CSH, and Bash scripts that integrate and orchestrate the flow. • Add support for new AI network configurations, hardware accelerator variants, reference builds, and EDA tool revisions. • Maintain current documentation, patches, reference configurations, and reproducible build instructions. • Identify, debug, and resolve automation, infrastructure, and tool-integration issues across the workflow. Performance and Power Collateral Generation • Generate complete performance and power collateral for each neural network processed through XNNC. • Collect and summarize:Cycle count, frames per second (FPS), and memory-bandwidth metrics from XTSC simulation.End-to-end performance metrics from Palladium emulation.Dynamic power estimates, including total and memory power, from Joules gate-level analysis. • Deliver results consistently across reference builds in standard formats, including cycle-count CSVs, power CSVs, and consolidated summary reports. • Validate result quality, consistency, and reproducibility before collateral is shared with stakeholders. Team Enablement and Support • Serve as the primary internal point of contact for users of the COLLATERAL-AUTO project. • Onboard new users and provide guidance on running the XNNC, Palladium, and Joules workflow. • Debug user runs and triage issues related to environments, scripts, CAD/EDA tools, and flow configuration. • Review performance and power summaries for correctness, completeness, and consistency. • Improve team-wide productivity by creating reusable guidance, troubleshooting documentation, and reliable reference workflows. Required Qualifications Experience • 10+ years of experience in various embedded software or general software development roles. • 3+ years of experience with AI frameworks, AI network compilation, or related tooling. • Experience with one or more of: TensorFlow, PyTorch, ONNX, Apache TVM, or AI network compilers. Technical Expertise • Strong Python scripting skills. • Proficiency with CSH and Bash shell scripting. • Working knowledge of JSON and automation-oriented configuration formats. • Understanding of hardware edge-AI accelerators, RTL execution flows, and performance analysis. • Familiarity with debugging complex software, toolchain, and multi-stage automation issues. Education • Bachelor’s or Master’s degree in Software Engineering, Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline. Preferred Qualifications • Experience using AI-assisted development tools for rapid prototyping and effective technical prompting. • Experience with Cadence tools, including Palladium and Joules, or equivalent EDA/emulation/power-analysis workflows. • Familiarity with IP design platforms, RTL simulation or emulation, gate-level power analysis, and AI accelerator validation. • Strong written communication skills for producing technical documentation, runbooks, and performance/power reports. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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