← Back to roles

Application Engineer - digital implementation

Cadence Design Systems, Inc.

YOKOHAMARTL / HDLPhysical designPosted Sep 21, 2026
Apply on Cadence Design Systems, Inc.

Overview

Open roles
679
At this company
See all
Similar roles
75
Same title, 16 companies
Search
Added in 30 days
679
At this company, still open

Skills named in this posting

  • STA
  • Place and route
  • Mixed-signal
  • Python
  • Tcl
  • Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus. 4. Assist in technical evaluation, assessment and delivery of concurrent mixed signal design. Position Requirements: • Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. • Requires working knowledge of one or more programming languages, and effective communication and soft skills. • An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product, ML/AI is a plus. • Good communication in English and good work attitude. • Be familiar with shell/Perl/Tcl/Python etc. script language. We’re doing work that matters. Help us solve what others can’t.

Apply on the employer's site

Original posting: cadence.wd1.myworkdayjobs.com

Apply on Cadence Design Systems, Inc.

RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

Same employer

View all 679