← Back to roles

Sr Principal Design Engineer

Cadence Design Systems, Inc.

BANGALORERTL / HDLVerificationPosted Sep 21, 2026
Apply on Cadence Design Systems, Inc.

Overview

Cadence Design Systems, Inc.
Open roles
678
At this company
See all
Similar roles
156
Same title, 18 companies
Search
Added in 30 days
678
At this company, still open

Skills named in this posting

  • Verilog
  • UVM
  • Formal verification
  • Tcl
  • Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently Should be good in Perl/Tcl scripting and automation We’re doing work that matters. Help us solve what others can’t.

Apply on the employer's site

Original posting: cadence.wd1.myworkdayjobs.com

Apply on Cadence Design Systems, Inc.

RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

Same employer

More roles at Cadence Design Systems, Inc.

View all 678