← Back to roles

Staff Engineer, RTL Design, AI Hardware

Tenstorrent

Belgrade, SerbiaRISC-VRTL / HDLCompilersPhysical designSoC / ASICPosted Oct 26, 2026
Apply on Tenstorrent

Overview

Open roles
123
At this company
See all
Added in 30 days
32
At this company, still open

Skills named in this posting

  • SystemVerilog
  • Verilog
  • Microarchitecture
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. You’ll join Tenstorrent’s AI Hardware team in Belgrade, building the silicon behind Tenstorrent’s custom AI platform. As a Staff RTL Design Engineer, you will contribute to the development of next-generation AI hardware by implementing and optimizing micro-architectures, improving performance and power efficiency, and collaborating across hardware teams. This role offers the opportunity to work on challenging, high-impact designs in a fast-paced environment. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are • An engineer with a demonstrated depth in digital design and micro-architecture, and ability to make architectural decisions and solve novel problems with broad downstream impact.. • Demonstrated hands-on expertise and ownership of complex designs through RTL, verification, implementation, and silicon or post-silicon debug where applicable. • Comfortable writing Verilog or SystemVerilog and interpreting synthesis and timing results. • Track record of delivering complex ASIC or accelerator hardware, with experience in providing technical direction, mentoring engineers and raising design quality across the team. What We Need • Engineers who own a coherent technical area or subsystem, implement and refine its micro-architectural features, influence its architecture and interfaces, and guide related implementation work across multiple contributors or teams. • Lead complex PPA trade-offs, make recommendations adopted across teams, and own the resulting technical outcome while balancing power, area, and frequency. • Drive alignment across RTL, DV, performance, physical design, software, and architecture, resolve interface or dependency conflicts, and establish a clear technical path forward. • Identify ambiguous or novel failure modes, coordinate root-cause analysis across teams, anticipate downstream impact, and drive corrective action through validation closure • Provide technical direction and mentorship to engineers, establish reusable design practices, review standards, and methodologies that improve quality and execution, and represent the team in architecture and cross-functional reviews, clearly communicating trade-offs, risks, and recommendations. What You Will Learn • Techniques for developing high-performance RTL targeting AI and ML workloads. • How power, performance, and area are balanced across design, verification, and physical implementation. • Tools and methods used to evaluate design trade-offs and optimize compute architectures. • What it takes to ship production-grade silicon that supports next-generation AI systems. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Apply on the employer's site

Original posting: job-boards.greenhouse.io

Apply on Tenstorrent

RISC-V ecosystem

Tenstorrent in the RISC-V ecosystem

RISC-V International: Premier Board

Tenstorrent builds AI/ML accelerators and RISC-V processors in the form of IP, chiplets, chips, and boards that are scalable from 8-wide for data centers to 2-wide for edge and embedded IoT solutions. | At Tenstorrent, we build chips to power the models of the future.

  • Tenstorrent designs both RISC-V CPU cores and AI accelerators, and licenses them as IP
  • Its TT-Ascalon RISC-V CPU family has third-party tool support (Ashling RiscFree debug and trace)
  • Powers what is described as the first automotive RISC-V AI accelerator chiplet

Same employer

View all 123