System Design Power Validation Engineer
Taiwan, TaipeiPosted Apr 16, 2026
Overview
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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU & SOC acts as the brains of computers, robots, and self-driving cars that can understand the world.
We are looking for Power Validation Engineer in Taipei for board/system power qualification and function test, responsible for NVIDIA Data Center platform, Graphics board, ARM Based platform and Autonomous Driving Platform. If you're creative and autonomous, we want to hear from you!What you'll be doing:
• DC-DC Power signal measurement.
• Power testing and debugging.
• Compensation tuning.
• Server/Motherboard/Mobile system functionality test.
• Partner with hardware design engineers on debug and FA.
• Co-work with mechanical/thermal engineers for cooler/heatsink design.
What we need to see:
• Bachelor/Master in EE, computer science, or relative majors.
• Familiar with Linux OS.
• Good English communication skills.
• Good PC system and Data center platform knowledge.
• 3+ years of experience
Ways to stand out from the crowd:
• Experience in measuring DC-DC power solution.
• Proactive personality.
• Good team player.
• Strong desire on creativity.
• Quick thinking.
Apply on the employer's site
Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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