Prinicipal Customer Engagement Engineer - PDK
SHANGHAIPosted Sep 21, 2026
Overview
- Added in 30 days
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- At this company, still open
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• Bachelor’s degree is required, with 6+ years of experience in IC design, electronic engineering, or computer science–related applications.
• Familiar with analog design flows, including circuit and layout design, physical verification (DRC/LVS/Dummy Fill), and post‑layout RC extraction flows.
• Solid understanding of Spice models and simulation flows is a strong plus.
• Basic understanding of semiconductor manufacturing processes (e.g., CMOS process fundamentals, PDK concepts, variability considerations).
• Experience supporting foundry is highly preferred.
• Proficient in programing languages, including PERL/TCL/SKILL., experience w/ Cadence PAS/Pcell Designer tool is a plus.
• Strong communication skills, self‑motivated, with a collaborative mindset and customer‑oriented attitude.
• MS degree and/or prior experience at an IC design house or foundry is a plus.
We’re doing work that matters. Help us solve what others can’t.
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Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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