Lead Product Engineer - Genus & Innovus
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- STA
- Place and route
- Low-power design (UPF)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities – Foundry Design Service Team Support
• Develop and maintain Genus‑to‑Innovus digital implementation reference flows for foundry design service teams.
• Support RTL synthesis, floorplanning, placement, CTS, routing, and physical optimization for production SoC designs.
• Provide methodology guidance on timing closure, congestion mitigation, and power‑aware implementation at advanced nodes.
• Support hierarchical and block‑based implementation flows used in design services and multi‑project environments.
• Diagnose and resolve convergence issues impacting timing, power, area, and routability in late design stages.
• Enable reusable, standardized implementation flows across multiple foundry design service programs.
Foundry Common Requirements – Genus & Innovus Enablement
• Support foundry‑preferred synthesis and place‑and‑route methodologies aligned with signoff expectations.
• Enable consistent constraint handling (SDC, UPF) across RTL synthesis and physical implementation stages.
• Support power‑intent driven implementation flows including low‑power optimization and power domain integration.
• Provide guidance on advanced‑node challenges such as routing congestion, multi‑patterning‑aware placement, and CTS robustness.
• Support integration of Genus and Innovus flows with signoff tools such as Tempus, Quantus, Voltus, and Pegasus.
• Assist design service teams with ECO implementation, late‑stage timing closure, and tapeout readiness.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
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