Principal Product Engineer – High-Speed IP UCIE

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview Join a growing and dynamic IP team developing best-in-class digital and mixed-signal IP solutions. This role focuses on post-sales technical support for high-performance interface IP, working as part of a team supporting UCIe, PCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, and HBM PHYs. The Principal Product Engineer is a key technical leader and product owner, responsible for driving product engineering activities across the full lifecycle—from pre-sales engagement and pre-silicon integration to post-silicon bring-up and customer deployment. This role serves as a primary interface between customers and Cadence R&D, leading technical discussions, resolving complex issues, and ensuring successful product adoption. This position requires strong technical depth, customer-facing leadership, excellent communication skills, and the ability to drive execution across global, cross-functional teams. Key Responsibilities • Act as the primary product engineering owner for UCIE die-to-die subsystems at the customer level • Lead customer engagements, drive technical discussions, design reviews, and deployment strategy • Own and drive resolution of complex subsystem integration and implementation issues • Lead SoC integration reviews covering PHY and controller subsystems • Provide technical leadership for RTL, gate-level simulations, and timing closure strategies • Define and drive improvements to integration methodologies, checklists, and customer collateral • Lead post-silicon bring-up and debug activities, ensuring successful customer deployment • Collaborate cross-functionally with R&D, validation, and applications teams to deliver product readiness • Drive continuous improvement in customer experience, turnaround time, and engineering quality • Mentor junior engineers and provide technical guidance across projects and teams • Leverage AI tools to improve debug efficiency, data analysis, and decision-making Position Requirements • Strong experience with high-speed interface IP • Deep understanding of RTL design, gate-level verification, and simulation methodologies • Experience with synthesis, STA, and timing closure; backend knowledge is a plus • Familiarity with DFT methodologies, test flows, and system validation approaches Skills & Qualifications [Required] • Bachelor’s in electrical engineering, Computer Engineering, or related field with 7+ years of experience, or Master’s with 5+ years, or PhD with relevant experience • Proven ability to solve complex technical problems and drive root cause to closure • Experience leading cross-functional technical efforts across design, validation, and customer teams • Strong communication skills with ability to influence customer and internal stakeholders • Experience managing multiple priorities, escalations, and technical reviews • Demonstrated ability to represent the organization in customer-facing technical roles • Strong ownership mindset and ability to drive deliverables independently [Preferred] • Experience with memory and/or high-speed communication interfaces (DDR, LPDDR, PCIe, Ethernet, UCIe, USB) • Understanding of analog/mixed-signal design practices • Experience in customer-facing silicon debug and bring-up environments • Familiarity with AI-assisted workflows and data-driven debug techniques We’re doing work that matters. Help us solve what others can’t.