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Senior/Staff Physical Design Engineer

MediaTek Inc

BangalorePhysical designSoC / ASICPosted Nov 4, 2026
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Skills named in this posting

  • STA
  • Place and route
  • Python
  • Tcl
  • Perl
Lead Block Coordinator (APR / Physical Design) — 10+Yrs (Innovus) • 10+ years of ASIC/SoC Physical Design / APR experience in a reputed product company, with multiple tapeouts. • Senior Block Coordinator responsible for planning/execution and closure of 15+ blocks. • Strong hands-on expertise in Cadence Innovus: floorplan, place/opt, CTS, route, and ECO closure at block level. • Proven ability to drive timing closure (setup/hold), MMMC, constraints/exceptions alignment, and QoR improvement across blocks. • Solid experience in congestion/routability debugging (macro placement/pin access/blockages/density) and driving closure actions with clear metrics. • Experience across advanced and lower/mature nodes (e.g., 2/3/4/6nm). • Strong understanding of block signoff readiness and coordination for DRC/LVS, SI-aware optimization, and IR/EM closure with signoff teams. • Mandatory scripting/automation: strong Tcl (Innovus) for flow execution, report parsing, and QoR tracking; Python/Perl/Shell preferred. • Strong cross-team coordination with STA/DFT/Synthesis/CAD.

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Original posting: careers.mediatek.com

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RISC-V ecosystem

MediaTek Inc in the RISC-V ecosystem

RISC-V International: Strategic

We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.

  • Named in coverage of RISE, the Linux Foundation Europe RISC-V Software Ecosystem project, and RISC-V edge-AI market analysis
  • Listed on the landscape as a RISC-V International member

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