FPGA Lead Engineer
Overview
Skills named in this posting
- SystemVerilog
- Verilog
- VHDL
- Place and route
- PCIe
- AMBA / AXI
- Ethernet
- I2C / UART
• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows.
• Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy.
• Drive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug.
• Drive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation.
• Design, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL.
• Develop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug.
• Support performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities.
• Define and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases.
• Support and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols.
• Provide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.
#LI-LL1
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Original posting: careers.mediatek.com
RISC-V ecosystem
MediaTek Inc in the RISC-V ecosystem
RISC-V International: Strategic
We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.
- Named in coverage of RISE, the Linux Foundation Europe RISC-V Software Ecosystem project, and RISC-V edge-AI market analysis
- Listed on the landscape as a RISC-V International member
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