Compiler Performance Engineer
PolandCompilersFirmwareFull TimePosted Oct 9, 2026
Overview
- Added in 30 days
- 482
- At this company, still open
Skills named in this posting
- Branch prediction
- Vector / SIMD
- x86
- C
- C++
- Python
- LLVM
- MLIR
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
SENIOR COMPILER PERFORMANCE ENGINEER
The Role:
This role focuses on improving application performance on AMD CPUs by analyzing compiler output, post‑link behavior, and machine‑code characteristics in real applications. You will work with AMD’s compiler and performance teams to identify inefficiencies in generated code, refine optimization pipelines (including MLIR/LLVM‑based transformations), and contribute targeted improvements that enhance execution on AMD architectures. The position involves deep technical analysis of proprietary workloads, collaboration with internal specialists, and delivering actionable guidance that strengthens AMD’s performance position across key software partners.
Key Responsibilities:
• Analyze compiler generated x86 64 machine code to identify inefficiencies and missed optimizations.
• Work with MLIR and LLVM IR to inspect transformations, diagnose issues, and improve lowering behavior.
• Develop or refine MLIR/LLVM optimization passes that enhance performance on AMD architectures.
• Refactor C/C++ code to improve auto vectorization, loop transformations, and memory access patterns.
• Use profiling tools to identify performance bottlenecks at the IR, compiler, or binary level.
• Collaborate with AMD compiler specialists on instruction selection, register allocation, and optimization heuristics and post-link optimization.
Preferred Experience:
• Experience analyzing performance issues in compiler pipelines or generated binaries.
• Strong knowledge of LLVM, MLIR, and modern compiler optimization techniques.
• Solid C/C++ programming skills with an emphasis on compiler friendly code.
• Ability to read and understand x86 64 assembly, including SIMD instructions.
• Familiarity with profiling tools (perf, VTune, MSVC profiler).
• Understanding of CPU architecture fundamentals (pipelines, caches, branch prediction).
• Experience with Git or similar version control systems.
Bonus Experience:
• Hands on experience with SIMD intrinsics (SSE, AVX, AVX2, AVX 512).
• Knowledge of concurrency and threading APIs.
• Experience with binary level tools (objdump, perf annotate, LLVM MCA).
• Familiarity with Python or JavaScript for tooling.
• Comfort working in both Linux and Windows environments.
Academic Credentials:
At least a BS/MS in computer science, computer engineering or a related field.
#LI-SF1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
SENIOR COMPILER PERFORMANCE ENGINEER
The Role:
This role focuses on improving application performance on AMD CPUs by analyzing compiler output, post‑link behavior, and machine‑code characteristics in real applications. You will work with AMD’s compiler and performance teams to identify inefficiencies in generated code, refine optimization pipelines (including MLIR/LLVM‑based transformations), and contribute targeted improvements that enhance execution on AMD architectures. The position involves deep technical analysis of proprietary workloads, collaboration with internal specialists, and delivering actionable guidance that strengthens AMD’s performance position across key software partners.
Key Responsibilities:
• Analyze compiler generated x86 64 machine code to identify inefficiencies and missed optimizations.
• Work with MLIR and LLVM IR to inspect transformations, diagnose issues, and improve lowering behavior.
• Develop or refine MLIR/LLVM optimization passes that enhance performance on AMD architectures.
• Refactor C/C++ code to improve auto vectorization, loop transformations, and memory access patterns.
• Use profiling tools to identify performance bottlenecks at the IR, compiler, or binary level.
• Collaborate with AMD compiler specialists on instruction selection, register allocation, and optimization heuristics and post-link optimization.
Preferred Experience:
• Experience analyzing performance issues in compiler pipelines or generated binaries.
• Strong knowledge of LLVM, MLIR, and modern compiler optimization techniques.
• Solid C/C++ programming skills with an emphasis on compiler friendly code.
• Ability to read and understand x86 64 assembly, including SIMD instructions.
• Familiarity with profiling tools (perf, VTune, MSVC profiler).
• Understanding of CPU architecture fundamentals (pipelines, caches, branch prediction).
• Experience with Git or similar version control systems.
Bonus Experience:
• Hands on experience with SIMD intrinsics (SSE, AVX, AVX2, AVX 512).
• Knowledge of concurrency and threading APIs.
• Experience with binary level tools (objdump, perf annotate, LLVM MCA).
• Familiarity with Python or JavaScript for tooling.
• Comfort working in both Linux and Windows environments.
Academic Credentials:
At least a BS/MS in computer science, computer engineering or a related field.
#LI-SF1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Apply on the employer's site
Original posting: careers.amd.com
RISC-V ecosystem
Advanced Micro Devices (AMD) in the RISC-V ecosystem
RISC-V International: Strategic
For more than 45 years AMD has driven innovation in high-performance computing, graphics, and visualization technologies; the building blocks for gaming, immersive platforms, and the data center.
- Ships MicroBlaze V, a RISC-V soft-processor core for AMD FPGAs/adaptive SoCs (docs, Vitis quick-start guide, BSP macros)
- amd.com states AMD has been a RISC-V member since 2020
- ROCm/LLVM docs include a RISC-V code-generation target; RISC-V debug support in AMD tools
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