Design Verification Technical Manager (High-Speed IO: PCIe & USB)

Role Overview We are seeking two Senior Design Verification Engineers to architect and execute comprehensive verification strategies for our next-generation high-performance SoCs. In this role, you will take technical ownership of IP-level and subsystem-level verification for mission-critical high-speed serial protocols, specifically PCIe and USB. Beyond standard UVM and constrained-random methodologies, you will be a catalyst for modernizing our verification flow—integrating AI/LLM-assisted workflows to accelerate test writing, assertion generation, log triage, and coverage closure. Key Responsibilities 1.Testbench Architecture & Test Planning a. Define, author, and review detailed Verification Plans (vPlans) from architectural and micro-architectural specifications through tape-out sign-off. b. Architect, build, and maintain modular, scalable, and reusable UVM-based testbenches from scratch, including custom drivers, monitors, scoreboards, predictors, and reference models. c. Drive constrained-random test generation, SystemVerilog Assertions (SVA), and functional coverage metrics to achieve 100% coverage sign-off. 2.High-Speed Subsystem & Protocol Verification a. Lead IP- and subsystem-level verification for PCIe (Gen 4/5/6) and USB (USB 3.2 / USB4 / Type-C) controllers and PHY interfaces (PIPE/UTMI). b. Verify complex protocol dynamics, including: i. Link Training and Status State Machine (LTSSM) transitions and recovery loops. ii. Low-power states (ASPM L0s, L1, L1.1/L1.2, USB U1/U2/U3) and power management handshakes. iii. Equalization, credit flow control, split transactions, packet ordering, and error injection/recovery flows. iv. Integrate and debug industry-standard Verification IPs (VIPs) from leading vendors (Synopsys, Cadence, Avery/Siemens). 3.Automation, Tooling & Infrastructure a. Build scripts for regression health monitoring, automated failure extraction, seed sweeping, and automated coverage report merging. b. Collaborate closely with Design, Emulation, Firmware, and Post-Silicon Validation teams to debug complex system-level failures. 4.AI & LLM-Augmented Verification Workflows a. Actively deploy and refine LLM-assisted techniques to accelerate the DV lifecycle: b. Leverage AI tools to generate boilerplate UVM components, corner-case test vectors, and SVA properties from design specs. c. Implement automated triage agents using LLMs to ingest simulation log files, pinpoint root-cause failure signatures, and summarize crash states. d. Optimize prompt engineering and programmatic interfaces (APIs, CLI scripts) to build reproducible team-wide verification copilots.