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Principal Product Engineer - Innovus+

Cadence Design Systems, Inc.

GYEONGGI-DO (Seoul)CompilersPosted Sep 21, 2026
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overall Description We are seeking a Product Engineer to drive innovation in Cadence Innovus+ and our agentic AI platform integration. In this role, you will be at the forefront of enhancing the Innovus+ digital implementation tool with advanced agentic AI capabilities. You will focus on leveraging Innovus+ with our agentic AI platform to enhance product capabilities, support R&D initiatives, and deliver exceptional value to early-engagement customers. Your responsibilities will include developing agentic workflows that streamline design processes, providing technical support to resolve customer issues, and collaborating with cross-functional teams to continuously improve the integration and usability of the tool. Minimum Requirements • Bachelor's degree in Electrical Engineering or a closely related field • 5+ years of hands-on experience with Innovus, Fusion Compiler, or IC Compiler II • Strong understanding of digital implementation and signoff flows • Excellent analytical and problem-solving skills • Fluent verbal and written communication in English Preferred Requirements • 8+ years of professional experience in semiconductor design tools and flows • Proven experience with 4nm or newer process technologies • Strong knowledge of Large Language Models (LLMs) and artificial intelligence technologies • Familiarity with agentic AI systems and their applications We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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