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133 results · page 3 of 6 · dates: UTC

Senior CPU Design Verification Engineer
SiFive
2026-09-02
Hyderabad, IndiaRISC-VRTL / HDLVerificationSoC / ASIC2026-09-02
Staff Design Verification Engineer
SiFive
2026-09-02
Hyderabad, IndiaRISC-VRTL / HDLVerificationSoC / ASIC2026-09-02
Staff Formal Verification Engineer
SiFive
2026-09-02
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLVerification2026-09-02
Power Infrastructure Engineer
SiFive
2026-08-30
Santa Clara, California, United StatesRISC-VRTL / HDLSoC / ASICFPGA2026-08-30
Design Verification Infrastructure Engineer - Platform
SiFive
2026-08-30
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-30
Product Power Engineer
SiFive
2026-08-29
Santa Clara, California, United StatesRISC-VRTL / HDLSoC / ASICFPGA2026-08-29
Product Power Engineer
SiFive
2026-08-29
Santa Clara, California, United StatesRISC-VRTL / HDLSoC / ASICFPGA2026-08-29
Power Model Engineer
SiFive
2026-08-29
Santa Clara, California, United StatesRISC-VRTL / HDLSoC / ASICFPGA2026-08-29
Power Infrastructure Lead
SiFive
2026-08-29
Santa Clara, California, United StatesRISC-VRTL / HDLSoC / ASICFPGA2026-08-29
Technical Program Manager
SiFive
2026-08-21
Bengaluru, IndiaRISC-V2026-08-21
Senior / Staff Design Verification Engineer
SiFive
2026-08-21
Ahmedabad, IndiaRISC-VRTL / HDLVerificationFirmware2026-08-21
Zebu flow Engineer
SiFive
2026-08-20
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLFPGA2026-08-20
Senior RTL Design Engineer - CPU Frontend
SiFive
2026-08-18
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-18
Senior Full Stack Engineer
SiFive
2026-08-17
Hsinchu, TaiwanRISC-V2026-08-17
Software Engineer - FPGA-Accelerated RTL Simulation
SiFive
2026-08-17
Berkeley, California, United StatesRISC-VRTL / HDLCompilersSoC / ASIC2026-08-17
Design Verification Engineer to Staff Engineer (Unit Level Test)
SiFive
2026-08-13
Hsinchu, TaiwanRISC-VRTL / HDLVerificationCompilers2026-08-13
Principal Design Verification Engineer – CPU Coherent Interconnect
SiFive
2026-08-12
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationSoC / ASIC2026-08-12
Interconnect Design Engineer
SiFive
2026-08-08
Hsinchu, TaiwanRISC-VRTL / HDLVerificationCompilers2026-08-08
Power Management Design Engineer
SiFive
2026-08-08
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-08-08
Power Management Design Engineer
SiFive
2026-08-08
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-08-08
Full-Stack Staff Engineer
SiFive
2026-08-07
Hyderabad, IndiaRISC-V2026-08-07
Staff RTL Design Engineer
SiFive
2026-08-06
Hsinchu, TaiwanRISC-VRTL / HDLVerificationPhysical design2026-08-06
Staff System Validation Engineer
SiFive
2026-08-04
Hsinchu, TaiwanRISC-VRTL / HDLVerificationSoC / ASIC2026-08-04
Staff Design Verification Engineer – Cache Verification
SiFive
2026-08-04
Hsinchu, TaiwanRISC-VRTL / HDLVerificationSoC / ASIC2026-08-04
Staff Design Verification Engineer – Cache Verification
SiFive
2026-08-04
Hsinchu, TaiwanRISC-VRTL / HDLVerificationSoC / ASIC2026-08-04