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133 results · page 4 of 6 · dates: UTC

Senior Design Verification Engineer – High Performance CPU Core
SiFive
2026-08-04
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-04
Staff Design Verification Engineer – High Performance CPU Core
SiFive
2026-08-04
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-04
Senior Design Verification Engineer – High Performance CPU Core
SiFive
2026-08-04
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-04
Staff Design Verification Engineer – High Performance CPU Core
SiFive
2026-08-04
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-04
Staff Design Verification Engineer – High Performance CPU Core
SiFive
2026-08-04
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-04
Core Performance Architect
SiFive
2026-08-04
Santa Clara, California, United StatesRISC-VRTL / HDLFPGA2026-08-04
Core Performance Architect
SiFive
2026-08-04
Santa Clara, California, United StatesRISC-VRTL / HDLFPGA2026-08-04
Core Performance Architect
SiFive
2026-08-04
Santa Clara, California, United StatesRISC-VRTL / HDLFPGA2026-08-04
Intern - Design Verification Infrastructure Engineer - Platform
SiFive
2026-08-01
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationCompilers2026-08-01
Performance Architect
SiFive
2026-07-31
Hsinchu, TaiwanRISC-V2026-07-31
Strategic Sales Director
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-V2026-07-31
Director of Sales, Commercial Accounts
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-V2026-07-31
Senior Design Verification Engineer
SiFive
2026-07-31
Hsinchu, TaiwanRISC-VRTL / HDLVerificationCompilers2026-07-31
Design Verification Infrastructure Engineer - Software
SiFive
2026-07-31
Hsinchu, TaiwanRISC-VRTL / HDLVerification2026-07-31
Software Engineer - Platform Technologies
SiFive
2026-07-31
Austin, Texas, United StatesRISC-V2026-07-31
Staff RTL Design Engineer - CPU Midcore
SiFive
2026-07-31
Cambridge, England, United KingdomRISC-VRTL / HDLVerificationCompilers2026-07-31
Java VM Software Performance Analysis Engineer
SiFive
2026-07-31
Hsinchu, TaiwanRISC-VCompilersFPGA2026-07-31
Workload / Performance Model Lead
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLCompilersFirmware2026-07-31
SOC Architect
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VKernel / LinuxFirmwareSoC / ASIC2026-07-31
Core Performance Architect
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLFPGA2026-07-31
System Validation Engineer to Staff Engineer
SiFive
2026-07-31
Hsinchu, TaiwanRISC-VRTL / HDLVerificationSoC / ASIC2026-07-31
Staff Engineer - Design Verification
SiFive
2026-07-31
Hyderabad, IndiaRISC-VRTL / HDLVerification2026-07-31
Principal Design Verification Engineer – High Performance CPU Subsystem
SiFive
2026-07-31
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
Senior Staff Engineer, Physical Design - NoC
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLPhysical design2026-07-31
Staff Design Verification Engineer – Coherent Interconnect
SiFive
2026-07-31
Boston, Massachusetts, United StatesRISC-VRTL / HDLVerificationSoC / ASIC2026-07-31