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3,268 results · page 97 of 131 · dates: UTC

Staff Engineer - DV
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLVerification2026-07-31
Staff RTL Design Engineer - CPU LS/PF/MMU
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-07-31
Senior Staff Verification Engineer For Worldguard
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLVerification2026-07-31
Staff Engineer, Physical Design - Cores
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLPhysical design2026-07-31
Senior Staff Design Verification Engineer – Coherent Interconnect
SiFive
2026-07-31
Boston, Massachusetts, United StatesRISC-VRTL / HDLVerificationSoC / ASIC2026-07-31
Senior Staff Design Verification Engineer – Coherent Interconnect
SiFive
2026-07-31
Boston, Massachusetts, United StatesRISC-VRTL / HDLVerificationSoC / ASIC2026-07-31
Principal Interconnect Design Engineer
SiFive
2026-07-31
Santa Clara, CARISC-VRTL / HDLVerificationCompilers2026-07-31
Staff / Sr. Staff Engineer DV
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLVerification2026-07-31
Staff Engineer, Physical Design
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLCompilersPhysical design2026-07-31
Staff Engineer, Physical Design
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLCompilersPhysical design2026-07-31
Platform Technologies Language & Frontend Design Engineer
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
CPU Design Verification Engineer
SiFive
2026-07-31
Hyderabad, IndiaRISC-VRTL / HDLVerification2026-07-31
Senior Design Verification Infrastructure Engineer - VIPs and Testbench
SiFive
2026-07-31
Bengaluru, Karnataka, IndiaRISC-VRTL / HDLVerification2026-07-31
Principal Design Verification Engineer – CPU Core LSU
SiFive
2026-07-31
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
Principal Design Verification Engineer – CPU Core Hardware Prefetch
SiFive
2026-07-31
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
Principal Design Verification Engineer – CPU Core Frontend
SiFive
2026-07-31
Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
Senior Staff Software Quality Assurance Engineer
SiFive
2026-07-31
Hsinchu, TaiwanRISC-VRTL / HDLCompilersFirmware2026-07-31
Datacenter System Software Architect
SiFive
2026-07-31
Santa Clara, CARISC-VRTL / HDLKernel / LinuxFirmware2026-07-31
Confidential Computing Software Architect
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationFirmware2026-07-31
Linux Kernel Architect
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLKernel / LinuxSoC / ASIC2026-07-31
CPU Power-Management Design Engineer
SiFive
2026-07-31
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-07-31
2027 Term 1 Internship – IC Design Exploration Intern
Advanced Micro Devices (AMD)
2026-07-31
Singapore, SingaporeRTL / HDLVerificationCompilersPhysical design2026-07-31
Senior ASIC Verification Engineer - PMU
NVIDIA Corporation
2026-07-31
China, ShanghaiRISC-VRTL / HDLVerificationSoC / ASIC2026-07-31
Senior Chip Design and Verification Engineer
NVIDIA Corporation
2026-07-31
Israel, Tel AvivRTL / HDLVerification2026-07-31
Senior Circuit Design Engineer - Power Modeling and Simulation
NVIDIA Corporation
2026-07-31
US, CA, Santa Clara, US, CA, RemoteRemoteRTL / HDL2026-07-31