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9 results · dates: UTC

• S

  Technical Engineering Intern - Design for Test (DFT) Internship

  Synopsys

  2026-10-22

  Ho Chi Minh City, VietnamCompilersSoC / ASIC2026-10-22
• 

  Intern: AI for Smarter ATE Test Development & Debug

  Cadence Design Systems, Inc.

  2026-10-21

  VALBONNE (Sophia)Firmware2026-10-21
• 

  Intern: AI for Silicon Test Data Analytics & Failure Analysis

  Cadence Design Systems, Inc.

  2026-10-21

  VALBONNE (Sophia)2026-10-21
• 

  [NanoIC topic] Electrical Test Structure Design for Advanced Interconnects

  imec

  2026-10-17

  Master internship - Leuven2026-10-17
• 

  Design and Implementation of a Test Protocol Description Language for IEEE Std 1838 Flexible Parallel Ports

  imec

  2026-10-17

  Master internship - LeuvenRTL / HDLSoC / ASIC2026-10-17
• R

  Test Equipment Design Intern (Onsite)

  RTX

  2026-09-21

  US-CT-EAST HARTFORD-J ~ 400 Main St ~ BLDG J2026-09-21
• 

  Design For Test Intern, MS - Summer 2027

  Marvell Asia PTE Ltd

  2026-09-17

  Santa Clara, CARTL / HDLSoC / ASIC2026-09-17
• 

  Design for Test Intern, BS - Summer 2027

  Marvell Asia PTE Ltd

  2026-09-06

  Morrisville, NCVerificationSoC / ASIC2026-09-06
• 

  NVIDIA 2027 Internships: Hardware Design for Test (DFT)

  NVIDIA Corporation

  2026-08-19

  US, CA, Santa ClaraPhysical design2026-08-19