Serdes IP Design Engineer
Synopsys
Wuhan, ChinaRTL / HDLPhysical designSoC / ASIC2026-11-07
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Serdes IP Design Engineer
Synopsys
Wuhan, ChinaRTL / HDLPhysical designSoC / ASIC2026-11-07Principal D2D SerDes & Analog Layout Design Engineer
Microsoft Corporation
United States, California, Mountain ViewPhysical designSoC / ASIC2026-11-04Principal Analog IC Design Engineer, High Speed SerDes
Cadence Design Systems, Inc.
SAN JOSE2026-10-21Principal Analog IC Design Engineer, High Speed SerDes
Cadence Design Systems, Inc.
SAN JOSE2026-10-19SerDes IP Systems Engineering Director
Cadence Design Systems, Inc.
SAN JOSE2026-10-09Principal Validation and Hardware Design Engineer (SerDes)
Marvell Asia PTE Ltd
Santa Clara, CA2026-10-08Serdes IP Design Engineer
Synopsys
Wuhan, ChinaRTL / HDLPhysical designSoC / ASIC2026-09-30Principal Product Engineer – High-Speed IP SerDes
Cadence Design Systems, Inc.
GYEONGGI-DO (Seoul)RTL / HDLPhysical designSoC / ASIC2026-09-21- MilpitasRTL / HDL2026-07-01
- Irvine, CARTL / HDLFirmware2026-05-05
Serdes Digital IC Design Engineer
MediaTek Inc
HsinChuSoC / ASIC2026-03-29- HsinChuRTL / HDLVerification2026-03-08
- Irvine, CA2025-12-11
- HsinChuRTL / HDLVerification2024-07-23
