Physical design, place-and-route, timing closure and backend flows.
Roles 1,981–2,010 of 2,038, newest first.
Senior / Principal Physical Design Engineer About Fractile Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet
Introduction Edgecortix Inc. is seeking a Hardware Design Engineer with proven RTL/logic and ASIC design expertise. If you have a strong desire to build state-of-the-art digital chips and systems join us and let's reshape the future of AI.
Introduction We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team. The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to synthesis, timing c
Introduction We are seeking a highly motivated Front-End Design Engineer (RTL Integration) to join our Artificial Intelligence Hardware Team at EdgeCortix. In this role, you will take ownership of integrating our proprietary Dynamic Neural
EdgeCortix
Introduction We are seeking an experienced Physical Design Engineer to join our team developing next-generation AI acceleration SoCs and chiplets at EdgeCortix. In this role, you will play a key part in driving synthesis, timing closure, a
OmniDesign
Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Senior Design Engineer will be responsible for the RTL and FPGA design and v
OmniDesign
The Senior Analog IC Design Engineer will be working on one or two of the following: 1. high speed SerDes, 2. PLL, Oscillators, 3. PMU, 4. Data Converters Should be familiar with Analog design for 1 or two of the ares mentioned abov
OmniDesign
Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. Omni Design is developing exciting high-speed Mixed-Signal SOC. We are looking f
OmniDesign
Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Manager of digital and mixed-signal engineering will be responsible for deve
Unisoc (Shanghai) Technologies Co., Ltd.
1、完成模块从算法/协议到架构的实现； 2、完成模块的RTL实现及相关验证工作； 3、完成模块的PPA（Performance，Power，Area）优化； 4、参与算法/协议/架构的评估与优化； 5、参与模块的FPGA验证及芯片调试； 6、参与技术方向的规划和解决方案的评估。 1、电子/信息相关专业，硕士及以上学历，3年及以上工作经历； 2、精通verilog RTL描述语言； 3、熟悉数字电路设计和验证方法学； 4、熟悉EDA工具和脚本语言； 5、熟悉视频标准或图像处理
Join the leading chiplet startup! As an Eliyan DFT Implementation lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturabili
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software
Unisoc (Shanghai) Technologies Co., Ltd.
1. ASIC IC 设计芯片后端工程师从RTL2GDSII 2. 布局布线，电源网络设计，时序收敛，功耗分析，物理验证等 任职要求硕士学位，微电子，计算机相关专业 1. 具有复杂数字后端设计的RTL2GDS工作经验 2. 具备完整的芯片Tapeout经验，后端布局规划（模块级或全芯片级） 3. 熟悉STA静态时序分析及低功耗设计与分析 4. 物理验证能力LVS/DRC/ERC/LVL/RTO/ANT/LUP 5. 具备熟练的脚本技能（比如TCL，Perl，Python，及
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
MediaTek Inc
1. Chip/SoC integration 2. Package/Floorplan integration #LI-LL1
MediaTek Inc
1. Work on 7nm~3nm physical design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issue
MediaTek Inc
1. Architecture design and digital circuit design. 2. RTL implementation and verification. 3. SoC chip integration from RTL to gate level including timing closure and testability 4. Design methodology and integration flow improvement #LI-L
MediaTek Inc
1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow
MediaTek Inc
1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flo
MediaTek Inc
1. Work on physical design implementation, methodology, and sign-off. 2. Perform floorplan, clock planning, place and route, timing closure, and physical verification. 3. Team work to finish project 4. Programming skill was needed to accomp
❓ About SiPearl… SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medica
What MatX Is Building MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking a Physical Design CAD Engineer to join our
What MatX Is Building MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join o
MediaTek Inc
1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flo
MediaTek Inc
1. (Internal transfer preferred, offers a platform for growth, optimizing cross-product workflow) 2. Personality: leadership, proactive, lead the team or task force to complete tough missions 3. Scope: Digital SOC design/integration, includ
Atmosic
At Atmosic, we are re-architecting wireless connectivity solutions from the ground up to radically reduce IoT device dependence on batteries. We aim to make batteries last forever and the Internet of Things battery free – thus breaking the
MediaTek Inc
1. Develop scalable platform clocking architecture for automotive SoC 2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 3. Drive clock architecture and designs to optimize power, perform
Unisoc (Shanghai) Technologies Co., Ltd.
1、完成模块从算法/协议到架构的实现； 2、完成模块的RTL实现及相关验证工作； 3、完成模块的PPA（Performance，Power，Area）优化； 4、参与算法/协议/架构的评估与优化； 5、参与模块的FPGA验证及芯片调试； 6、参与技术方向的规划和解决方案的评估。 • 画像処理/ビデオ/ディスプレイ関連のアルゴリズム&仕様定義のマイクロアーキテクチャの設計 • ブロック及びトップレベルの RTL 実現、最適化、検証の開発 • PPA（パフォーマンス、電力、面積
