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Physical design jobs 2,027
Physical design, place-and-route, timing closure and backend flows.
Roles 2,011–2,027 of 2,027, newest first.
- Sunnyvale, CAPhysical designSoC / ASICApr 14, 2022
Digital Designer
Atmosic
RTL / HDLPhysical designSoC / ASICFeb 4, 2022Atmosic Technologies is looking for a digital design engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commensurate with experience. Respon
- RTL / HDLVerificationPhysical designJan 28, 2022
Senior Digital LC/MAC Designer Atmosic Technologies is looking for LC/MAC design engineers who are passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commen
- RTL / HDLPhysical designAug 25, 2021
Atmosic Technologies is looking for a senior physical design engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commensurate with experience.
Senior Digital Designer
Atmosic
RTL / HDLVerificationPhysical designAug 23, 2021Sr. Digital Design Engineer Atmosic is looking for a Sr. Digital Design Engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. You will provide technical leadership with prove
SoC Architect
VeriSilicon, Inc.
Austin, Texas, San Jose, CA, USFirmwarePhysical designSoC / ASICJul 1, 2021The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must be able to pri
Modem Digital Design Engineer (5G/6G)
MediaTek Inc
HsinChuPhysical designSoC / ASICMay 24, 2021Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1
Senior DFT Engineer
OmniDesign
BangaloreRTL / HDLPhysical designSoC / ASICMar 31, 2021We are looking for an experienced DFT engineer, who is capable of driving the required DFT flows for our digital designs. The ability to work closely with rtl and pnr design team to drive testability is a key feature of this role! Quali
- BangaloreRTL / HDLPhysical designMar 16, 2021
We are looking for an experienced place-and-route engineer, who is capable of driving the required digital backend flows to create our designs. The ability to work closely with rtl design team to understand partition architecture and driv
- BangaloreRTL / HDLVerificationPhysical designJun 21, 2020
Senior Digital Design Engineer focusing on the digital datapath of high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with syn
Digital/RTL IC Design Engineer
OmniDesign
BangaloreRTL / HDLPhysical designSoC / ASICJun 20, 2020Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R
Senior DFT(Design for Test) Engineer
VeriSilicon, Inc.
ChengduPhysical designJul 24, 2019• Complete DFT test plan definition. • Complete DFT logic design, including: memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing. • Complete DFT test pattern verification. • Complete DFT mode timing constraint,
Senior/Staff Digital Design Engineer
VeriSilicon, Inc.
ChengduRTL / HDLPhysical designJul 24, 2019Focus on analog/digital mixed IP and Chip design&implementation. The engineers need to act as a strong team member and contributor, who also need to collaborate with analog team and backend team. • Define IP block spec and micro-architectu
Engineer/Sr. Engineer of Design Implementation
VeriSilicon, Inc.
ShanghaiRTL / HDLPhysical designJul 9, 2019• Responsible for SDC and UPF/CPF development and debug. • Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation. • IP level and chip lev
Senior/Staff Engineer of IO Design
VeriSilicon, Inc.
ShanghaiPhysical designJul 9, 2019• Design General IO library and Customization IO library, provide instruction on layout work. • Design ESD cell and provide ESD guideline for different foundry and process node. • Provide whole chip ESD solution and pad cell floor plan on c
- MilpitasRTL / HDLPhysical designMay 17, 2018
Senior Digital/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include development and verification of the digital controller for high performance data conve
Senior Engineer Design
Infineon Technologies AG
Bangalore BTPPhysical designJan 1, 2000#WeAreIn to transform theoretical concepts into real hardware designs. Are you in? Your role Key responsibilities in your new role • Own and drive STA flow and signoff methodology for HOBTO and Bixby Creek platforms. • Develop, qualify, a