About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFiv
Verification jobs 2,280
Design verification and validation — UVM, formal methods and testbench engineering.
Roles 1,381–1,410 of 2,280, newest first.
- Santa Clara, California, United StatesRISC-VRTL / HDLVerificationAug 30, 2026
Engineering Manager, AI Compiler Analysis
NVIDIA Corporation
US, CA, Santa Clara, US, TX, Austin, US, WA, SeattleVerificationCompilersAug 30, 2026NVIDIA's invention of the GPU transformed computer graphics, parallel computing, and modern AI. Today, NVIDIA high-performance processing platforms power breakthroughs across generative AI, autonomous systems, scientific computing, robotics
Chip Design Verification Engineer
NVIDIA Corporation
Israel, Tel AvivRTL / HDLVerificationAug 30, 2026We are now looking for a best-in-class Chip Design Verification Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer at NVIDIA's GPU-Networking group, you'll make a real impact in a dynamic, technology-
CPU Systems RTL Engineer
Qualcomm Technologies, Inc.
Santa Clara, California, United States of America, Austin, TX, USA, San Diego, CA, USA, Raleigh, NC, USARTL / HDLVerificationFirmwareAug 30, 2026Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this rol
CPU Micro-architect/RTL Designer (Multiple Locations)
Qualcomm Technologies, Inc.
Austin, Texas, United States of America, Santa Clara, California, United States of AmericaRTL / HDLVerificationPhysical designAug 30, 2026Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new p
Senior Physical Design Backend Engineer
NVIDIA Corporation
Israel, Tel AvivVerificationPhysical designAug 30, 2026NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency
- RTL / HDLVerificationSoC / ASICAug 30, 2026
Overview XCENA SoC의 ASIC Top을 integration하고, 검증합니다. XCENA 의 주요 IP는 주로 AXI Bus 상에서 동작하도록 구현되어 있으며, 이러한 AXI Bus 상의 IP 들을 통합하여 ASIC Top 설계를 수행합니다. ASIC Top integration 후, physical implementation을 위해 FPGA 합성(Xilinx Vivado 활용)이나 DC를 통한 ASIC 합성을
- RTL / HDLVerificationSoC / ASICAug 30, 2026
■ 회사 소개 엑시나(XCENA)는 AI 시대에 메모리의 역할을 새롭게 정의하는 반도체 팹리스 기업이다. 개방형 표준인 CXL(Compute Express Link)을 기반으로 AI 인프라의 메모리 확장성과 활용 효율을 높이는 차세대 메모리 디바이스를 제공한다. 이를 바탕으로 AI 인프라의 성능을 높이고 지연시간과 에너지 소비를 줄여 TCO(총소유비용)를 절감한다. 엑시나는 삼성전자와 SK하이닉스 출신 반도체 설계 전문가들
- Toronto, CanadaVerificationAug 30, 2026
- VerificationAug 30, 2026
- VerificationAug 30, 2026
Verification Engineer
Speedata
VerificationAug 30, 2026Digital Verification Engineer
Snowcap Compute
Design VerificationVerificationAug 30, 2026- 深圳、上海、北京、西安、成都RTL / HDLVerificationSoC / ASICAug 30, 2026
岗位职责: • 参与智能网卡芯片IP级或SOC级功能验证; • 与IC设计工程师沟通,参与所负责的IP或SOC验证功能点分解和验证计划制定; • 基于UVM验证方法学,参与所负责IP或SOC级别的仿真验证环境搭建; • 使用SystemVerilog和C语言开发测试向量并进行回归测试; • 参与计划及实施各种覆盖率分析。 任职要求: • 熟悉 system Verilog, UVM 以及 formal 验证方法; • 有开发 scalable and port
Senior Verification Engineer - Core Testbench & DV Methodology Lead
Semidynamics Technology Services, S.L.
VerificationAug 30, 2026SoC Design Verification Engineer
Rebellions
RISC-VVerificationSoC / ASICAug 30, 2026About the Job Rebellions은 Chiplet/SOC를 검증할 SOC Design Verification (SOC-DV) 전문가를 찾고 있습니다. SOC-DV 직무는 CPU (ARM Cortex-A Series, RISC-V), HBM, High-speed I/O 등 시스템 전반에 대한 검증을 수행하는 직무입니다. Chiplet/SOC의 1차 검증은 Design Service Provider (DSP)가 담당
IP Design Verification Engineer
Rebellions
RTL / HDLVerificationAug 30, 2026About the Job Rebellions은 NPU를 검증할 IP Design Verification (IP-DV) 전문가를 찾고 있습니다. IP-DV 직무는 Rebellions이 직접 설계하는 Neural/Tensor Core, Proprietary Network-on-Chip, Data Processing for UCIe/Ethernet/PCIe/HBM/HBF등 다양한 유형의 IP들에 대하여 전통적인 UVM 기반 Con
Design Validation Engineer
Rebellions
VerificationFirmwareAug 30, 2026About the Job Rebellions은 추론용 NPU와 이를 기반하여 구축할 데이터센터급 Scale-up 구조에 대한 Validation 업무를 수행할 검증 전문가를 찾고 있습니다. 본 직무는 LLM Workload 구동에 필요한 필수 IP 컴포넌트들을 통합하고 (Proof-of-Concept Design), 시뮬레이션 기반 테스트벤치를 개발하여 검증한 후, 최종적으로는 전체 시스템의 기능과 성능을 조기에 확인하는
SoC/Top Design Engineer
Rebellions
RTL / HDLVerificationPhysical designAug 30, 2026About the Job As a SoC/Top Design Engineer, you will perform RTL integration and top-level design for complex SoC projects. This role involves defining system architecture, optimizing performance and power, and collaborating closely with v
Jr. SoC Verification(경력)
HyperAccel
VerificationSoC / ASICAug 30, 2026Sr. SoC Verification(경력)
HyperAccel
VerificationSoC / ASICAug 30, 2026- VerificationAug 30, 2026
- VerificationAug 30, 2026
Verification Engineer
Eridu AI
Saratoga, CAVerificationAug 30, 2026Senior Design Verification Engineer
Espressif Systems (Shanghai) Co., Ltd
SingaporeSingaporeVerificationAug 30, 2026- VerificationSoC / ASICAug 30, 2026
- VerificationSoC / ASICAug 30, 2026
SoC Design Verification Engineer – Open Chiplet Atlas (Experienced)
bos semiconductors
VerificationSoC / ASICAug 30, 2026- VerificationSoC / ASICAug 30, 2026
SoC Design Verification Engineer – DRAM (Experienced)
bos semiconductors
VerificationSoC / ASICAug 30, 2026