Design of channel for ultra-high-speed ADC

In this project, a channel of an ADC is to be designed in 22nm technology which can be time-interleaved to realize ultra-high-speed conversion speeds. For example. a 1GS/s, 10-12-bit channel can be parallellized 32 times to get a 32GS/s ADC. The work is to done in collaboration with a PhD, who takes care of the front-end design, and supervised by an imec researcher, experienced in high-speed ADC design. Type of internship : PhD internship Duration : 6 months Required educational background : Electrotechnics/Electrical Engineering Supervising scientist(s) : For further information or for application, please contact Lucas Moura Santana ( Lucas.MouraSantana@imec.be ) The reference code for this position is 2026-INT-234 . Mention this reference code in your application. Only for self-supporting students. Applications should include the following information: resume motivation current study Incomplete applications will not be considered