RF Interposer for High-Bandwidth Co-Packaged Optics
Overview
Skills named in this posting
- UCIe / chiplets
his Master’s thesis will investigate RF interposer technology as a heterogeneous integration platform for co-packaged optics . The work will explore system architectures integrating RF/electronic and photonic chiplets and will focus on the design, modeling, and optimization of high-speed interconnects and critical integration structures. Key parameters such as insertion loss, return loss, bandwidth, crosstalk, routing density, and integration constraints will be evaluated. The project will combine electromagnetic simulation with system-level analysis to identify key design trade-offs and develop guidelines for RF-interposer-enabled CPO architectures . The outcome will provide insight into how RF interposer technology can support the evolution from compact optical-engine integration toward scalable, high-bandwidth optical connectivity for future AI systems . This direction is consistent with current research examining CPO as an enabling technology for high-performance computing and AI. Co-packaged optics for high-performance computing and artificial intelligence. Type of internship : Master internship Duration : 6-12 months Required educational background : Electrotechnics/Electrical Engineering, Physics, Nanoscience & Nanotechnology University promotor : Nadine Collaert (VUB) Supervising scientist(s) : For further information or for application, please contact Xiao Sun ( Xiao.Sun@imec.be ) The reference code for this position is 2026-INT-338 . Mention this reference code in your application. Applications should include the following information: resume motivation current study Incomplete applications will not be considered
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Original posting: imec-int.com
RISC-V ecosystem
imec in the RISC-V ecosystem
RISC-V International: Community
Interuniversity Microelectronics Centre is an international research & development organization, active in the fields of nanoelectronics and digital technologies.
- RISC-V research/design: system-level integration of a digital AI accelerator with RISC-V
- Participates in RISC-V automotive and space-chip ecosystem work
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