RTL Design Engineer
Overview
- Added in 30 days
- 16
- At this company, still open
Skills named in this posting
- SystemVerilog
- Verilog
- Low-power design (UPF)
- Microarchitecture
- PCIe
- UCIe / chiplets
- Ethernet
- SerDes
About EdgeQ
EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.
Experience: 3–15 Years
Location: Bangalore, India
Job Description
EdgeQ is looking for talented RTL Design Engineers across experience levels to join our design team developing high-performance, power-efficient semiconductor solutions for 5G/6G, edge computing, and networking applications. We are looking for engineers who are passionate about building high-performance and power-efficient silicon and can take ownership of RTL development from specification through implementation and tape out.
Responsibilities
• Design and develop synthesizable RTL using Verilog/System Verilog based on architectural and microarchitectural specifications.
• Work on microarchitecture, RTL coding, lint, CDC, synthesis, timing, and design-quality closure.
• Optimize designs for power, performance, and area (PPA).
• Debug RTL and simulation issues and work closely with verification, architecture, physical design, DFT, and firmware teams.
• Participate in IP/subsystem integration, design reviews, and tape out activities.
• Develop reusable and high-quality RTL following established design methodologies.
Required Skills
• Strong fundamentals in digital design and computer architecture.
• Hands-on experience with Verilog/System Verilog RTL design.
• Experience with ASIC/SoC development and related RTL design flows.
• Strong debugging and problem-solving skills.
Good to Have
Experience with any of the following - 5G/6G, RISC-V, O-RAN/eCPRI, JESD204, Ethernet, PCIe, UCIe, SerDes, DSP/data-path design, low-power design, or other high-speed interfaces.
Education
B.Tech/M.Tech/M.S./PhD in Electrical/Electronics Engineering, VLSI, Computer Engineering, or a related field.
Apply Now
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Original posting: edgeq.io
RISC-V ecosystem
EdgeQ in the RISC-V ecosystem
Base station-on-a-chip · RF · US · founded 2018
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