Design Verification Engineer

About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices. Experience: 3–15 Years Location: Bangalore, India Job Description EdgeQ is looking for talented Design Verification Engineers across experience levels to join our verification team working on complex semiconductor designs for 5G/6G, edge computing, and networking applications. We are looking for engineers who are passionate about building robust verification environments and ensuring high-quality silicon through comprehensive IP, SoC, and post-silicon verification. The role covers verification at IP, subsystem, SoC, and post-silicon levels. Responsibilities • Develop and execute verification strategies for digital IPs, subsystems, and complete SoCs. • Develop testbenches, test scenarios, sequences, checkers, scoreboards, assertions, and functional coverage. • Work with System Verilog and UVM to build scalable and reusable verification environments. • Verify complex data paths, control logic, memories, interfaces, and system-level functionality. • Perform block, IP, subsystem, and SoC-level verification including integration and system-level scenarios. • Debug simulation, formal, emulation, FPGA, and silicon issues and work closely with design and architecture teams. • Drive functional and code coverage closure and identify verification gaps. • Develop automation and verification infrastructure to improve regression, debug, and overall verification efficiency. • Support pre-silicon verification, silicon bring-up, post-silicon validation, and debug activities. Required Skills • Strong fundamentals in digital design and computer architecture. • Hands-on experience with Verilog/System Verilog and verification methodologies. • Experience with System Verilog/UVM-based verification environments. • Good understanding of constrained-random verification, assertions, functional coverage, and regression. • Strong debugging and problem-solving skills. • Experience with ASIC/SoC verification flows. • Verify low-power designs and power-management features using UPF, including power domains, isolation, retention, power states, and power sequencing. Good to Have Experience with any of the following - 5G/6G, RISC-V, O-RAN/eCPRI, JESD204, Ethernet, PCIe/CXL, UCIe, SerDes, Network-on-Chip (NoC), DSP/data path verification, low-power verification, formal verification, emulation/FPGA validation, or post-silicon debug. Education B.Tech/M.Tech/M.S. in Electrical/Electronics Engineering, VLSI, Computer Engineering, or a related field. Apply Now