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Senior DFT(Design for Test) Engineer

VeriSilicon, Inc.

ChengduPhysical designPosted Jul 24, 2019
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VeriSilicon, Inc.
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Skills named in this posting

  • DFT
• Complete DFT test plan definition. • Complete DFT logic design, including: memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing. • Complete DFT test pattern verification. • Complete DFT mode timing constraint, support DFT mode timing closure. • Support chip bring-up, complete test pattern debugging, yield improvement. • Provide technical support for customer/FAE/sales.

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Original posting: verisilicon.com

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RISC-V ecosystem

VeriSilicon, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

VeriSilicon is a Silicon Platform as a Service company that provides world class SoC and SiP solutions and a leading IP provider with IP portfolios address markets including mobile internet devices, datacenters, the Internet of Things (IoT), automotive, industrial, and medical electronics.

  • VeriSilicon supplies the GPU, ISP and display IP that RISC-V SoCs integrate, plus custom silicon services
  • Its display processor IP was adopted in StarFive's RISC-V based JH-7110 vision platform
  • Canaan's RISC-V edge AIoT SoC adopted VeriSilicon ISP and GPU IPs, and its embedded GPU IP powers HPMicro's HPM6800 RISC-V MCU series

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