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Software Engineer II

Cadence Design Systems, Inc.

SAN JOSERTL / HDLPhysical designFull timePosted Nov 6, 2026
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Skills named in this posting

  • Place and route
  • C
  • C++
  • Python
  • Tcl
  • Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated Software Engineer II to join the Innovus R&D team. Innovus is Cadence’s flagship digital implementation platform, enabling customers to design advanced semiconductor chips from RTL to GDSII. In this role, you will contribute to the development of advanced routing technologies for digital physical design, with an emphasis on structural routing including bus routing and constrained routing. You will work closely with experienced R&D engineers to develop algorithms and software solutions for challenging routing problems in advanced semiconductor designs. Key Responsibilities • Design and implement algorithms for advanced bus routing and constrained routing • Develop high-performance and scalable software using C/C++ on Linux/UNIX platforms • Debug routing issues and improve quality of results, runtime, and robustness • Collaborate with R&D teams to define requirements, validate solutions, and deliver production-quality features Minimum Qualifications • MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field • Strong programming skills in C/C++ • Strong foundation in algorithms, data structures, and problem-solving • Good understanding of software development and debugging in Linux/UNIX environments • Strong analytical and debugging skills • Ability to work effectively in a collaborative, team-oriented environment Preferred Qualifications • Coursework, research, internship, or project experience in VLSI CAD, physical design, algorithms, computational geometry, or optimization • Basic knowledge of digital IC design or physical design concepts • Experience with algorithm development or large-scale software development • Familiarity with scripting languages such as Tcl, Python, or Perl • Exposure to EDA tools or place-and-route flows is a plus, but not required The annual salary range for California is $105,000 to $195,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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