Senior Researcher in Wireless Digital Baseband & Low-MAC (FPGA/ASIC)

Ghent University – imec IDLab Research group IDLab is an imec research group embedded at Ghent University and the University of Antwerp, focusing on internet technologies, wireless communication systems, and data science. It brings together more than 300 researchers and data scientists from over 40 nationalities, combining expertise in connectivity, distributed systems, and artificial intelligence. At Ghent University, IDLab conducts research across the domains of internet technology and connectivity on the one hand, and data science and artificial intelligence on the other. Its activities span the full innovation stack, ranging from fundamental models and algorithms to system design and real-world applications, addressing challenges in areas such as telecommunications, smart environments, industry, mobility, and healthcare. IDLab is part of imec, a world-leading research and innovation hub in nanoelectronics and digital technologies. Imec enables end-to-end innovation by combining expertise in hardware, software, and system design, supporting the development of next-generation communication and intelligent systems. The group benefits from a unique and extensive experimental research infrastructure, including wireless testbeds, IoT and robotics laboratories, and large-scale validation environments, allowing researchers to validate new concepts under realistic conditions and transition from software prototypes to real-world systems. What you will do Future wireless intelligent distributed communication systems for emerging applications such as industrial automation, robotics and mission critical communication require highly efficient real-time communication stacks. Moving from software-defined prototypes toward embedded and ASIC-ready designs demands expertise in digital baseband processing, low-level MAC, and hardware acceleration. This position focuses on the design, implementation, and optimization of wireless digital radio stacks on FPGA, supporting the evolution of Device-to-Device (D2D) and multi-RAT communication systems from SDR to ASIC-ready architectures. You will work within a multidisciplinary team building end-to-end wireless systems, closely collaborating with: A D2D protocol/software developer working on decentralized communication mechanisms, A hardware acceleration researcher focusing on AI/ML and system-level optimization, and System architects working on next-generation modular chiplet architectures. Job description The successful candidate will contribute to the hardware-centric implementation of next-generation wireless communication systems. Your main responsibilities include: Design and implementation of digital baseband (PHY) and low-level MAC functionalities on FPGA platforms (e.g., RFSoC) Translation of SDR-based algorithms (e.g., OFDM(A), synchronization, channel estimation) into hardware-efficient architectures Development of D2D communication components, including decentralized access and synchronization mechanisms Implementation of multi-RAT capabilities (e.g., 5G NR, WiFi) Optimization of designs for latency, throughput, and resource utilization Contribution to hardware/software co-design and functional partitioning between CPU, FPGA, and future ASIC implementations Support the migration from FPGA prototypes toward ASIC-ready designs, including fixed-point optimization and quantization Integration with higher-layer protocols, AI-driven modules, and system-level components Validation and benchmarking on embedded hardware platforms in challenging use cases This is a hands-on research position, covering the full research and development cycle, with a strong focus on building proof-of-concept prototypes, transforming software-based systems into hardware-efficient implementations. Who you are Required qualifications PhD (or equivalent experience) in Electrical Engineering, Telecommunications, Computer Engineering, or a related field Strong background in digital communications and signal processing Hands-on experience with FPGA design (VHDL/Verilog/SystemVerilog or HLS) Experience in wireless PHY implementation (e.g., OFDM, synchronization, channel estimation) Understanding of MAC layer design and real-time system constraints Familiarity with SDR platforms (e.g., RFSoC, USRP) Knowledge of fixed-point design and hardware constraints Strong programming skills (C/C++, Python, Linux environments) Strong collaboration and communication skills Key system-level requirement Ability to reason about end-to-end system design and HW/SW partitioning, including mapping time-critical functions to hardware and coordinating with software-based components Preferred profile Experience with 3GPP systems (e.g., 5G NR) or WiFi PHY/MAC design Experience with RFSoC or embedded FPGA platforms Familiarity with ASIC design flows or hardware implementation constraints Experience in hardware/software co-design and system integration Knowledge of multi-RAT systems and decentralized networking Interested? Start date: as soon as possible We offer a full-time position as a senior researcher Place of employment: Technologiepark-Zwijnaarde 126, 9052 Gent For further information, please contact Prof. Adnan Shahid , Ingrid Moerman , Dries Naudts , and/or Dr. Vasilis Maglogiannis