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Senior Verification Engineer

Accelercom

Cambridge, UKRTL / HDLVerificationSoC / ASICFPGAFull TimePosted Oct 1, 2026
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Skills named in this posting

  • UVM
Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP. Purpose Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out.

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Original posting: accelercomm.pinpointhq.com

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RISC-V ecosystem

Accelercom in the RISC-V ecosystem

5G physical layer for high-performance networks · RF · UK · founded 2016

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