高级数字芯片设计工程师(实现方向)6704
Overview
Skills named in this posting
- Verilog
- STA
- Python
- Tcl
- Perl
1、承担项目中SoC Implementation相关工作(Synthesis/ LEC/ CLP/STA),并保证按时高质量交付;
2、承担项目中Performance,Power,Area的优化工作;
3、配合SoC Designer对相关项目的RTL代码和SDC进行优化,保证代码和SDC符合implementation / DFT / 时序要求;
4、配合PnR进行STA和Timing ECO等相关工作,支持产品时序收敛,满足signoff需求。
1、通信、电子、计算机等相关专业本科及以上学历,3年以上行业相关工作经验;
2、熟练掌握Verilog / Tcl / Perl / python等相关脚本语言;
3、熟练掌握Synthesis/ LEC/CLP/ STA相关概念;
4、熟悉Synopsys / Cadence 主要EDA tool相关使用方法和flow,如PrimeTime / Genus等;
5、具备SoC / PnR相关芯片设计经验者优先;
6、具备良好的沟通能力和团队合作精神。
Apply on the employer's site
Original posting: wecruit.hotjob.cn
RISC-V ecosystem
Unisoc (Shanghai) Technologies Co., Ltd. in the RISC-V ecosystem
RISC-V International: Strategic
Unisoc, formerly Spreadtrum Communications, Inc., Unisoc has research centres in Shanghai, Beijing, Tianjin, Suzhou, Hangzhou, Chengdu, Xiamen, United States, Finland and India, technical support…
- Unisoc (Shanghai) is a large Chinese mobile/IoT chipset vendor listed as a RISC-V member
- Appears in RISC-V ecosystem coverage including a RISC-V ISA based DSP heading to mass production and RISC-V blockchain SIG activity
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