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Silicon Validation & Bring up Engineer

Lyte AI

Sunnyvale, CASoC / ASICPosted Oct 20, 2026
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Skills named in this posting

  • Mixed-signal
  • Ethernet
  • I2C / UART
  • Python
About the role • We are seeking a hands-on Validation Engineer to take our custom silicon devices from first power-on to production readiness. The role involves close collaboration across analog design, logic design, and package design teams.What you'll do • Lead silicon bring up for new tape-outs from initial power-on through functional validation • Develop and execute structured test plans covering functional and performance validation • Characterize analog and digital circuit behavior against product specifications • Build automated test infrastructure using Python for high-throughput characterization • Debug complex mixed-signal devices using oscilloscopes, logic analyzers, spectrum analyzers, and protocol analyzers • Validate high-speed interfaces including signal integrity analysis • Root-cause issues and distinguish design vs. process vs. board-level failuresRequired Qualifications • BS in Electrical Engineering, Computer Science, or a related field with 5+ years of relevant experience • Hands-on chip or system bringup and validation experience • Proficiency in Python for test automation and data analysis • Experience validating high-speed serial interfaces • Understanding of analog fundamentals: signal integrity, transmission lines, feedback theory, and voltage/current source compliance testing • Knowledge of frequency-domain and time-domain measurements • Solid analog circuit knowledge: bias networks, LDOs, PLLs, ADCs/DACs, and mixed-signal interfaces • Ability to read and interpret schematics, layout files, and datasheet specifications • SOC Circuitry: DMA, Cache, DDR, SRAM, IPC, Timers / PTP, OTP • Hands on experience with Digital comms: SPI, I2C, UART, Ethernet, CAN, SWD, JTAGPreferred Qualifications • MS or PhD in Electrical Engineering, Computer Science, or a related technical field • PVT corner characterization and yield analysis experience • Prior ASIC tape-out experience from prototype to production • Reliability testing exposure: HTOL, ELFR, ESD/latch-upBenefits (subject to location and local regulations) • Competitive salary and equity • Comprehensive medical, dental, and vision coverage • 401(k) retirement plan • Flexible vacation and time-off policy • Collaborative, fast-paced, and inclusive work environment • Opportunity to work on cutting-edge technologies with a highly cross-functional team

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Original posting: ats.rippling.com

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RISC-V ecosystem

Lyte AI in the RISC-V ecosystem

Perception layer for physical AI · AI · US · founded 2021

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