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Fine-Grained Mapping of AI Training & Inference Workloads Across the Full Memory Hierarchy

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Skills named in this posting

  • Performance modeling
  • C++
  • Python
Understanding this behavior m odern AI training and inference workloads is crucial for designing optimized memory hierarchies and minimizing data‑movement bottlenecks. In this internship, the student will develop a fine‑grained workload‑to‑memory mapping framework that characterizes how representative AI workloads interact with the entire memory stack. This includes profiling layer‑level and operator‑level footprints, traffic patterns, reuse distances, and temporal/spatial locality. By integrating these insights into a system‑level simulation environment, the student will evaluate bottlenecks, identify optimization opportunities, and generate actionable guidelines for future memory hierarchy design targeting large‑scale AI systems. Skills to stand out: Solid understanding of memory subsystem Familiarity with AI training and inference workload characteristics Strong programming skills in C++ or Python Experience with performance modelling techniques Exposure to system-level simulation tools or benchmarking frameworks is a plus (Ramulator, DRAMSys, DRAMSim, Gem5, …) Type of internship : Master internship, PhD internship Duration : 6-9 months Required educational background : Computer Science, Electrotechnics/Electrical Engineering, IT, Nanoscience & Nanotechnology Supervising scientist(s) : For further information or for application, please contact Khakim Akhunov ( Khakim.Akhunov@imec.be ) The reference code for this position is 2026-INT-045 . Mention this reference code in your application. Imec allowance will be provided for students studying at a non-Belgian university. Applications should include the following information: resume motivation current study Incomplete applications will not be considered

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Original posting: imec-int.com

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RISC-V International: Community

Interuniversity Microelectronics Centre is an international research & development organization, active in the fields of nanoelectronics and digital technologies.

  • RISC-V research/design: system-level integration of a digital AI accelerator with RISC-V
  • Participates in RISC-V automotive and space-chip ecosystem work

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