Evaluating Heterogeneous Computing Platforms for AI-RAN
PhD internship, Master internship - LeuvenPosted Oct 17, 2026
Overview
Skills named in this posting
- DDR / HBM
- C
- C++
- Python
- CUDA
- PyTorch / TensorFlow
Summary The evolution of Artificial Intelligence-enabled Radio Access Networks
(AI-RAN) is transforming traditional cellular base stations into distributed
computing platforms that integrate real-time radio communication, network
optimization, and AI-driven edge services. These platforms rely on
heterogeneous hardware, including CPUs, GPUs, specialized accelerators,
high-bandwidth memory, and high-speed interconnects. However, the coexistence
of latency critical radio functions and dynamic, compute and memory intensive
AI workloads present significant challenges in performance predictability,
resource utilization and energy efficiency. This internship aims to characterize representative AI-RAN workloads on
existing CPU/GPU/accelerator platforms to identify performance bottlenecks and
derive hardware architecture requirements for future AI-RAN nodes. Using
open-source software and experimental performance profiling, the student will
investigate workload execution, resource utilization, memory behaviour, data
movement, and interference between concurrent workloads. The collected
measurements will support a data-driven assessment of existing hardware
configurations, highlighting their limitations and potential improvements. The
expected outcome is a workload-to-architecture framework that translates
observed performance bottlenecks into recommendations for future heterogeneous
computing architectures, supporting more efficient, predictable, and scalable
AI-RAN infrastructure. Desirable skills
Programming: CUDA, C/C++.Python, GPU execution models,
Telecommunications: Understanding about 4G/5G RAN
architecture, PHY processing, radio resource management, or O-RAN
concepts. ( Exposure to Open-source RAN software like OpenAirInterface,
srsRAN, or related platforms is a plus point.)
AI/ML workloads: PyTorch, neural network inference, model
optimization, or AI acceleration.
Performance analysis: Linux perf, hardware counters,
memory-bandwidth analysis, latency profiling, or power measurement, NVIDIA
Nsight Systems, or Nsight Compute Type of internship : PhD internship, Master internship Duration : 6 Required educational background : Computer Science, Electrotechnics/Electrical Engineering, Other University promotor : Debjoti Bhattacharjee (KULeuven) Supervising scientist(s) : For further information or for application, please contact Udari De Alwis ( Udari.DeAlwis@imec.be ) The reference code for this position is 2026-INT-319 . Mention this reference code in your application. Imec allowance will be provided. Applications should include the following information: resume motivation current study Incomplete applications will not be considered
Apply on the employer's site
Original posting: imec-int.com
RISC-V ecosystem
imec in the RISC-V ecosystem
RISC-V International: Community
Interuniversity Microelectronics Centre is an international research & development organization, active in the fields of nanoelectronics and digital technologies.
- RISC-V research/design: system-level integration of a digital AI accelerator with RISC-V
- Participates in RISC-V automotive and space-chip ecosystem work
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